Field of the Invention
The present invention relates to a data communication system, and more particularly, to a data communication system for a high speed interface of a packet and a data transmission apparatus and a data reception apparatus of the data communication system.
Description of the Related Art
A liquid display device (LCD) panel or an organic light emitting diode (OLED) panel is mainly used for a display device for implementing a flat display.
The display device includes a timing controller, a source driver, and a display panel.
The timing controller provides display data to the source driver, wherein the source driver generates and outputs a source signal in correspondence to the data provided from the timing controller and the display panel drives a screen in correspondence to the source signal.
The display panel is developed in order to achieve a high resolution, and in order to support a high resolution of the display panel, the timing controller and the source driver need to be configured to communicate data through a high speed interface.
The timing controller and the source driver may use a protocol based on a delay locked loop (DLL) or a phase locked loop (PLL) for the purpose of a high speed interface. The DLL-based protocol may be understand to have a format in which the source driver may recover a received packet on the basis of the DLL, and the PLL-based protocol may be understand to have a format in which the source driver may recover a received packet on the basis of the PLL. As the DLL-based protocol, a clock embedded data signaling (CEDS) protocol may be exemplified. The CEDS protocol has a format in which a clock is embedded in data.
When the CEDS protocol is used, the timing controller configures and transmits a packet by combining a clock and data with each other, and the source driver receives the packet and recovers the clock and the data on the basis of the DLL. The source driver generates and outputs a source signal by using the recovered data and clock.
For a high speed interface, it is advantageous to configure a packet based on the PLL as compared with a case of configuring a packet based on the DLL.
When the timing controller and the source driver communicate with each other in the aforementioned environment, reception characteristics and clock data recovery characteristics of the source driver should be favorably guaranteed for the high speed interface.
However, when a packet is transmitted/received at a high speed, a packet including bits continuously keeping the same value may have an influence on a receiver output jitter, and each bit may not be easily recognized in a reception and clock data recovery process. For example, when a data value logically and continuously keeps “0” or “1” over several bits or more, since the receiver may not capture an exact timing of the packet and there is no change in a data value in the reception or clock data recovery process, it is difficult to exactly recognize each bit.
The aforementioned problem becomes an obstacle in a data communication system that implements a high speed interface between a data transmission apparatus and a data reception apparatus as well as the timing controller and the source driver.
In order to solve the aforementioned problem, the data communication system is required to use an improved protocol for a high speed interface between the data transmission apparatus such as the timing controller and the data reception apparatus such as the source driver.